Integrated circuit (“IC”) packages typically include dies coupled to a substrate. In conventional IC packages, to fill gaps between dies and a substrate in order to provide mechanical support, a gap-filling underfill material is provided. The gap-filling underfill material is made to occupy the gaps via capillary action. Specifically, the gap-filling underfill material is deposited adjacent the dies and flows to the space under the dies via capillary action.
There are many issues with this type of underfill process. One example of an issue is that there is a design trade-off between viscosity and coefficient of thermal expansion (“CTE”) of the underfill material. Specifically, a lower CTE is generally desirable in many instances, and lowering CTE is achieved by increasing the percentage of silica filler particles in the underfill material. However, increasing the amount of silica filler particles increases viscosity of the underfill material. Above a certain viscosity, the underfill material will not properly flow under the dies via capillary action. Another example of an issue is that, due to the nature of the capillary underfill process, various die placement constraints must be observed. For example, different types of dies may have a particular required clearance that may be unacceptably high. Additionally, dummy dies may need to be placed in order to mitigate the effects of warpage or other effects. The above issues present difficulties in designing and manufacturing die packaging.